 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATA SHEET MOS INTEGRATED CIRCUIT PD75P3036 4-BIT SINGLE-CHIP MICROCONTROLLER The PD75P3036 replaces the PD753036's internal mask ROM with a one-time PROM or EPROM. Because the PD75P3036 supports programming by users, it is suitable for use in prototype testing for system development using the PD753036 and for use in small-scale production. * Caution The PD75P3036KK-T is not designed to guarantee the reliability required for use in massproduction. Please use it only for performance evaluation during testing and test production runs. Detailed descriptions of functions are provided in the following document. Be sure to read the document before designing. PD753036 User's Manual : U10201E FEATURES * Compatible with PD753036 * Internal PROM: 16384 x 8 bits * PD75P3036KK-T : Reprogrammable (ideally suited for system evaluation) * PD75P3036GC, 75P3036GK : One-time programmable (ideally suited for small-scale production) * Internal RAM: 768 x 4 bits * Can operate in the same power supply voltage as the mask version PD753036 * VDD = 1.8 to 5.5 V * LCD controller/driver * A/D converter Caution Mask-option pull-up resistors are not provided in this device. ORDERING INFORMATION Part Number Package 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5-mm pitch) 80-pin ceramic WQFN Internal PROM One-time PROM One-time PROM EPROM Quality Grade Standard Standard Not applicable PD75P3036GC-3B9 PD75P3036GK-BE9 * PD75P3036KK-T Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions. The information in this document is subject to change without notice. Document No. U11575EJ1V0DS00 (1st edition) (Previous No. IP-3657) Date Published November 1996 P Printed in Japan The mark * shows major revised points. (c) 1996 PD75P3036 Functional Outline Parameter Instruction execution time Function * 0.95, 1.91, 3.81, 15.3 s (main system clock: during 4.19-MHz operation) * 0.67, 1.33, 2.67, 10.7 s (main system clock: during 6.0-MHz operation) * 122 s (subsystem clock: during 32.768-kHz operation) PROM RAM General purpose register 16384 x 8 bits 768 x 4 bits * 4-bit operation: 8 x 4 banks * 8-bit operation: 4 x 4 banks 8 20 8 8 Also used for segment pins 13 V withstand voltage On-chip pull-up resistors can be specified by using software: 27 Internal memory Input/ output port CMOS input CMOS input/output Bit port output * N-ch open-drain input/output pins Total LCD controller/driver 44 * Segment selection: * Display mode selection: 12/16/20 segments (can be changed to bit port output in unit of 4; max. 8) Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) Timer 5 channels * 8-bit timer/event counter: 3 channels (16-bit timer/event counter, carrier generator, timer with gate) * Basic interval/watchdog timer: 1 channel * Watch timer: 1 channel * 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit * 2-wire serial I/O mode * SBI mode 8-bit resolution: 8 channels 16 bits * , 524, 262, 65.5 kHz (main system clock: during 4.19-MHz operation) * , 750, 375, 93.8 kHz (main system clock: during 6.0-MHz operation) * 2, 4, 32 kHz (main system clock: during 4.19-MHz operation or subsystem clock: during 32.768-kHz operation) * 2.86, 5.72, 45.8 kHz (main system clock: during 6.0-MHz operation) External: 3, Internal: 5 External: 1, Internal: 1 * Ceramic or crystal oscillator for main system clock oscillation * Crystal oscillator for subsystem clock oscillation STOP/HALT mode VDD = 1.8 to 5.5 V * 80-pin plastic QFP (14 x 14 mm) * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) * 80-pin ceramic WQFN Serial interface A/D converter Bit sequential buffer (BSB) Clock output (PCL) Buzzer output (BUZ) Vectored interrupt Test input System clock oscillator Standby function Power supply voltage Package * 2 PD75P3036 CONTENTS 1. PIN CONFIGURATION (Top View) ............................................................................................... 4 2. BLOCK DIAGRAM ......................................................................................................................... 6 3. PIN FUNCTIONS ............................................................................................................................ 7 3.1 3.2 3.3 3.4 Port Pins ................................................................................................................................................ 7 Non-port Pins ........................................................................................................................................ 9 Pin Input/Output Circuits ...................................................................................................................... 11 Recommended Connection of Unused Pins ...................................................................................... 14 4. Mk I MODE AND Mk II MODE SELECTION FUNCTION .............................................................. 15 4.1 4.2 Difference between Mk I Mode and Mk II Mode .................................................................................. 15 Setting of Stack Bank Selection Register (SBS) ................................................................................ 16 5. DIFFERENCES BETWEEN PD75P3036 AND PD753036 ........................................................ 17 6. PROGRAM COUNTER (PC) AND MEMORY MAP ....................................................................... 18 6.1 6.2 6.3 Program Counter (PC) .......................................................................................................................... 18 Program Memory (PROM) .................................................................................................................... 18 Data Memory (RAM) .............................................................................................................................. 20 7. INSTRUCTION SET ....................................................................................................................... 21 8. PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................................. 30 8.1 8.2 8.3 Operation Modes for Program Memory Write/Verify ......................................................................... 30 Program Memory Write Procedure ...................................................................................................... 31 Program Memory Read Procedure ...................................................................................................... 32 * * * * * 9. PROGRAM ERASURE (PD75P3036KK-T ONLY) ...................................................................... 33 10. OPAQUE FILM ON ERASURE WINDOW (PD75P3036KK-T ONLY) ......................................... 33 11. ONE-TIME PROM SCREENING .................................................................................................... 33 12. ELECTRICAL SPECIFICATIONS .................................................................................................. 34 13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ........................................................... 49 14. PACKAGE DRAWINGS ................................................................................................................. 51 15. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 54 APPENDIX A. FUNCTION LIST OF PD75336, 753036, AND 75P3036 .......................................... 55 APPENDIX B. DEVELOPMENT TOOLS ............................................................................................ 56 APPENDIX C. RELATED DOCUMENTS ............................................................................................ 60 3 PD75P3036 1. PIN CONFIGURATION (Top View) * 80-pin plastic QFP (14 x 14 mm) PD75P3036GC-3B9 * 80-pin plastic TQFP (fine pitch) (12 x 12 mm) PD75P3036GK-BE9 * 80-pin ceramic WQFN PD75P3036KK-T S31/BP7 S30/BP6 S29/BP5 S28/BP4 S27/BP3 S26/BP2 S25/BP1 S24/BP0 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 60 2 59 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 RESET X2 X1 VPP XT2 XT1 VDD AVREF AVSS AN5 AN4 AN3 43 19 42 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AN2 AN1 AN0 P83/AN7 P82/AN6 P81/TI2 P80/TI1 P33/MD3 P32/MD2 P31/SYNC/MD1 P30/LCDCL/MD0 P23/BUZ P22/PCL/PTO2 P21/PTO1 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1 Caution Connect the VPP pin directly to VDD. 4 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P40/D0 P41/D1 P42/D2 P43/D3 VSS P50/D4 P51/D5 P52/D6 P53/D7 P00/INT4 P01/SCK P02/SO/SB0 PD75P3036 PIN IDENTIFICATIONS P00 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P73 P80 to P83 BP0 to BP7 KR0 to KR7 SCK SI SO SB0, SB1 AVREF AVSS AN0-AN7 MD0 to MD3 D0 to D7 : Port0 : Port1 : Port2 : Port3 : Port4 : Port5 : Port6 : Port7 : Port8 : Bit Port0-7 : Key Return 0-7 : Serial Clock : Serial Input : Serial Output : Serial Bus 0,1 : Analog Reference : Analog Ground : Analog Input 0-7 : Mode Selection 0-3 : Data Bus 0-7 S12 to S31 VLC0 to VLC2 BIAS LCDCL SYNC TI0 to TI2 PTO0 to PTO2 BUZ PCL INT2 X1, X2 XT1, XT2 RESET VPP VDD VSS : Segment Output 12-31 : LCD Power Supply 0-2 : LCD Power Supply Bias Control : LCD Clock : LCD Synchronization : Timer Input 0-2 : Programmable Timer Output 0-2 : Buzzer Clock : Programmable Clock : External Test Input 2 : Main System Clock Oscillation 1, 2 : Subsystem Clock Oscillation 1, 2 : Reset : Programming Power Supply : Positive Power Supply : Ground COM0 to COM3 : Common Output 0-3 INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 5 PD75P3036 2. BLOCK DIAGRAM TI0/P13 PTO0/P20 AN0-AN5 AN6/P82 AN7/P83 8 AVREF AVSS 8-BIT TIMER/EVENT COUNTER #0 INTT0 TOUT0 A/D CONVERTER BASIC INTERVAL TIMER/ WATCHDOG TIMER INTBT INTT1 PROGRAM COUNTER (14) ALU SP (8) CY SBS BANK PORT0 4 P00-P03 PORT1 4 P10-P13 PORT2 4 P20-P23 PORT3 4 P30/MD0P33/MD3 P40/D0P43/D3 P50/D4P53/D7 PORT4 4 TI1/P80 PTO1/P21 TI2/P81 PTO2/PCL/P22 8-BIT TIMER/EVENT CASCADED COUNTER #1 16-BIT TIMER/ 8-BIT EVENT TIMER/EVENT COUNTER COUNTER #2 INTT2 BUZ/P23 WATCH TIMER INTW fLCD PORT5 GENERAL REG. PROM PROGRAM MEMORY 16384 x 8 BITS 4 PORT6 4 P60-P63 DECODE AND CONTROL PORT7 RAM DATA MEMORY 768 x 4 BITS 4 P70-P73 PORT8 4 P80-P83 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI TOUT0 12 S12-S23 S24/BP0S31/BP7 COM0COM3 VLC0-VLC2 BIAS LCDCL/P30 SYNC/P31 8 LCD CONTROL4 LER/ DRIVER 3 fLCD INT0/P10 INT1/P11 INT4/P00 INT2/P12 KR0/P608 KR7/P73 INTERRUPT CONTROL fx/2 N CPU CLOCK BIT SEQ. BUFFER (16) SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER CONTROL CONTROL SUB MAIN PCL/P22 XT1 XT2 X1 X2 VPP VDD VSS RESET 6 PD75P3036 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 P31 P32 P33 P40 Note 2 I/O I/O I/O I/O Input I/O I/O I/O Input Alternate function INT4 SCK SO/SB0 SI/SB1 INT0 INT1 INT2 TI0 PTO0 PTO1 PCL/PTO2 BUZ LCDCL/MD0 SYNC/MD1 MD2 MD3 D0 D1 D2 D3 I/O D4 D5 D6 D7 This is an N-ch open-drain 4-bit I/O port (PORT5). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (upper 4 bits) for program memory (PROM) write/verify. High impedance M-E This is an N-ch open-drain 4-bit I/O port (PORT4). When set to open-drain, voltage is 13 V. Also functions as data I/O pin (lower 4 bits) for program memory (PROM) write/verify. Yes High impedance M-E This is a programmable 4-bit I/O port (PORT3). Input and output can be specified in bit units. Connection of an on-chip pull-up resistor can be specified in 4-bit units by software. No Input E-B This is a 4-bit I/O port (PORT2). Connection of an on-chip pull-up resistor can be specified in 4-bit units by software. No Input E-B This is a 4-bit input port (PORT1). Connection of an on-chip pull-up resistor can be specified in 4-bit units by software. P10/INT0 can select noise elimination circuit. No Input Function This is a 4-bit input port (PORT0). Connection of an on-chip pull-up resistor can be specified in 3-bit units by software for P01 to P03. 8-bit I/O No Status after reset Input I/O circuit typeNote 1 * * P41 Note 2 P42 Note 2 P43 Note 2 P50 Note 2 P51 Note 2 P52 Note 2 P53 Note 2 Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. Low level input leakage current increases when input instructions or bit manipulate instructions are executed. 7 PD75P3036 3.1 Port Pins (2/2) Pin name P60 P61 P62 P63 P70 P71 P72 P73 P80 P81 P82 P83 BP0 BP1 BP2 BP3 BP4 BP5 BP6 BP7 I/O I/O I/O I/O Alternate function KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 TI1 TI2 AN6 AN7 Output S24 S25 S26 S27 Output S28 S29 S30 S31 These pins are also used as 1-bit I/O port (BIT PORT) segment output pin. No Note 2 H-A This is a 4-bit I/O port (PORT8). Connection of an on-chip pull-up resistor can be specified in 4-bit units by software. No Input Y-B Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. * * 2. BP0 through BP7 select VLC1 as an input source. However, the output levels change depending on the external circuit of BP0 through BP7 and VLC1. Example Because BP0 through BP7 are mutually connected inside the PD75P3036, the output levels of BP0 through BP7 are determined by R1, R2, and R3. PD75P3036 VDD R2 BP0 ON VLC1 R1 ON BP1 R3 8 PD75P3036 3.2 Non-port Pins (1/2) Pin name TI0 TI1 TI2 PTO0 PTO1 PTO2 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 Output Output I/O I/O I/O Input Input Output I/O Input Alternate function P13 P80 P81 P20 P21 P22/PCL P22/PTO2 P23 P01 P02 P03 P00 P10 Clock output Frequency output (for buzzer or system clock trimming) Serial clock I/O Serial data output Serial data bus I/O Serial data input Serial data bus I/O Edge detection vectored interrupt input (valid for detecting both rising and falling edges) Edge detection vectored interrupt input (detected edge is selectable) INT0/P10 can select noise elimination circuit. Noise elimination circuit /asynchronous is selectable Asynchronous Rising edge detection test input Parallel falling edge detection test input Parallel falling edge detection test input Ceramic/crystal oscillation circuit connection for main system clock. If using an external clock, input to X1 and input inverted phase to X2. Crystal oscillation circuit connection for subsystem clock. If using an external clock, input to XT1 and input inverted phase to XT2. XT1 can be used as a 1-bit (test) input. System reset input (low level active) Mode selection for program memory (PROM) write/verify Asynchonous Input Input Input -- -C INT1 INT2 KR0 to KR3 KR4 to KR7 X1 X2 XT1 XT2 RESET MD0 MD1 MD2, MD3 D0 to D3 D4 to D7 VPP -- I/O Input Input Input Input -- Input -- Input I/O P11 P12 P60 to P63 P70 to P73 -- -- -- -- -- P30/LCDCL P31/SYNC P32, P33 P40 to P43 P50 to P53 -- -- -- -- Input E-B Data bus for program memory (PROM) write/verify Input M-E Programmable power supply voltage for program memory (PROM) write/verify. For normal operation, connect to VDD. Apply +12.5 V for PROM write/verify. Positive power supply Ground -- -- VDD VSS -- -- -- -- -- -- -- -- Note Circuit types enclosed in brackets indicate Schmitt trigger input. 9 PD75P3036 3.2 Non-port Pins (2/2) Pin name S12 to S23 S24 to S31 I/O Output Alternate function -- Segment signal output Segment signal output Common signal output Power source for LCD driver Output for external split resistor cut Clock output for driving external expansion driver Clock output for synchronization of external expansion driver Analog signal input for A/D converter Function Status after reset Note 1 Note 1 Note 1 -- High impedance Input Input Input I/O circuit type G-A H-A G-B -- -- E-B E-B Y Y-B Output BP0 to BP7 -- -- -- COM0 to COM3 Output VLC0 to VLC2 BIAS LCDCLNote 2 SYNC Note 2 -- Output Output P30/MD0 Output P31/MD1 Input P82 P83 -- -- -- -- -- AN0 to AN5 AN6 AN7 AVREF AVSS A/D converter reference voltage A/D converter reference GND potential -- -- Z-N Z-N Notes 1. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs. S12 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 2. These pins are provided for future system expansion. Currently, only P30 and P31 are used. 10 PD75P3036 3.3 Pin Input/Output Circuits The input/output circuits for the PD75P3036's pins are shown in schematic form below. (1/3) TYPE A VDD data P-ch IN output disable N-ch TYPE D VDD P-ch OUT N-ch CMOS standard input buffer Push-pull output that can be set to output high-impedance (with both P-ch and N-ch OFF). TYPE E-B VDD P.U.R. P.U.R. enable P-ch TYPE B IN data Type D output disable IN/OUT Type A Schmitt trigger input with hysteresis characteristics. P.U.R. : Pull-Up Resistor TYPE B-C TYPE E-E VDD P.U.R. VDD P.U.R. enable P.U.R. data P-ch P.U.R. enable Type D output disable Type A IN/OUT P-ch IN P.U.R. : Pull-Up Resistor Type B P.U.R. : Pull-Up Resistor 11 PD75P3036 (2/3) TYPE F-A VDD P.U.R. P.U.R. enable data Type D output disable Type B VLC2 P.U.R. : Pull-Up Resistor N-ch IN/OUT OUT COM or SEG data N-ch P-ch P-ch TYPE G-B * P-ch N-ch VLC0 VLC1 TYPE F-B VDD P.U.R. P.U.R. enable output disable (P) data output disable output disable (N) N-ch VDD P-ch IN/OUT P-ch TYPE H-A * Type G-A IN/OUT SEG data Bit Port data output disable Type E-B P.U.R. : Pull-Up Resistor TYPE G-A * VLC0 VLC1 P-ch N-ch TYPE M-C VDD P.U.R. P.U.R. enable P-ch IN/OUT OUT data output disable N-ch N-ch SEG data VLC2 N-ch P.U.R. : Pull-Up Resistor 12 PD75P3036 (3/3) TYPE M-E * VDD P-ch Note TYPE Y-B IN/OUT N-ch (+13 V withstand voltage) data Type D P.U.R. output disable Type A port Note input Type Y P.U.R. : Pull-Up Resistor TYPE Z-N VDD data output disable input instruction P.U.R. enable P-ch IN/OUT Voltage limitation circuit (+13 V withstand voltage) Note The pull-up resistor operates only when an input instruction is executed (current flows from VDD to the pin when the pin is low). TYPE Y * AVREF VDD IN VDD AVSS reference voltage (from voltage tap of series resistor string) P-ch N-ch Sampling C + - reference voltage AVSS input enable ADEN N-ch AVSS Note Becomes active when an input instruction is executed. 13 PD75P3036 * 3.4 Recommended Connection of Unused Pins Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 Connect to VSS Recommended connection Connect to VSS or VDD Connect to VSS or VDD via a resistor individually P10/INT0 to P12/INT2 Connect to VSS or VDD P13/TI0 P20/PTO0 P21/PTO1 P22/PTO2/PCL P23/BUZ P30/LCDCL P31/SYNC P32, P33 P40 to P43 P50 to P53 P60/KR0 to P63/KR3 P70/KR4 to P73/KR7 P80/TI1 P81/TI2 P82/AN6 P83/AN7 S12 to S23 S24/BP0 to S31/BP7 COM0 to COM3 VLC0 to VLC2 BIAS XT1Note XT2 Note Input status : connect to VSS or VDD via a resistor individually. Output status: open Connect to VSS Input status : connect to VSS or VDD via a resistor individually. Output status: open Open Connect to VSS Connect to VSS only when VLC0 to VLC2 are all not used. In other cases, leave open. Connect to VSS or VDD Open Connect to VSS or VDD Connect to VDD directly AN0 to AN5 VPP Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor). 14 PD75P3036 4. Mk I MODE AND Mk II MODE SELECTION FUNCTION Setting a stack bank selection (SBS) register for the PD75P3036 enables the program memory to be switched between Mk I mode and Mk II mode. This function is applicable when using the PD75P3036 to evaluate the PD753036. When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for PD753036) When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for PD753036) 4.1 Difference between Mk I Mode and Mk II Mode Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the PD75P3036. Table 4-1. Difference between Mk I Mode and Mk II Mode Item Program counter Program memory (bytes) Data memory (bits) Stack Stack bank No. of stack bytes Instruction BRA !addr1 instruction CALLA !addr1 instruction Instruction CALL !addr instruction 3 machine cycles 2 machine cycles When set to Mk I mode for PD753036 4 machine cycles 3 machine cycles When set to Mk II mode for PD753036 PC13-0 16384 768 x 4 Selectable via memory banks 0 to 2 2 bytes Not available 3 bytes Available Mk I Mode Mk II Mode execution time CALLF !faddr instruction Supported mask ROM versions * Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore, this mode is effective for enhancing software compatibility with products exceeding 16 Kbytes. When the Mk II mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important than software compatibility. 15 PD75P3036 4.2 Setting of Stack Bank Selection Register (SBS) Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing this. The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be sure to initialize the stack bank selection register to 10xxBNote at the beginning of the program. When using the Mk II mode, be sure to initialize it to 00xxBNote. Note Set the desired value for xx. Figure 4-1. Format of Stack Bank Selection Register Address F84H 3 SBS3 2 SBS2 1 SBS1 0 SBS0 Symbol SBS Stack area specification 0 0 1 1 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Setting prohibited 0 Be sure to enter "0" for bit 2. Mode selection specification 0 1 Mk II mode Mk I mode Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in Mk I mode. When using instructions for Mk II mode, set SBS3 to "0" and set Mk II mode before using the instructions. 2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after RESET input and after setting the stack bank selection register. 16 PD75P3036 5. DIFFERENCES BETWEEN PD75P3036 AND PD753036 The PD75P3036 replaces the internal mask ROM in the program memory of the PD753036 with a one-time PROM or EPROM. The PD75P3036's Mk I mode supports the Mk I mode in the PD753036 and the PD75P3036's Mk II mode supports the Mk II mode in the PD753036. Table 5-1 lists differences among the PD75P3036 and the PD753036. Be sure to check the differences among these products before using them with PROMs for debugging or prototype testing of application systems or, later, when using them with a mask ROM for full-scale production. As to CPU function and on-chip hardware, see the User's Manual. Table 5-1. Differences between PD75P3036 and PD753036 Item Program counter Program memory (bytes) 14 bits 16384 Mask ROM Data memory (x 4 bits) Mask option Pull-up resistor of ports 4, 5 Split resistor for LCD driving power supply Selection of Yes (can select either 217 /fX or 2 15/fX)Note oscillation stabilization wait time Selection of subsystem clock feedback resistor Pin configuration Pin No. 29 to 32 Pin No. 34 to 37 Pin No. 50 Pin No. 51 Pin No. 52 Pin No. 53 Pin No. 69 Other Yes (can select either use enabled or use disabled) P40 to P43 P50 to P53 P30/LCDCL P31/SYNC P32 P33 IC No (fixed to 215/fX)Note 768 Yes (can specify whether to incorporate on-chip or not) No (don't incorporate on-chip) 16384 One-time PROM, EPROM PD753036 PD75P3036 No (use enabled) P40/D0 to P43/D3 P50/D4 to P53/D7 P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2 P33/MD3 VPP Noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts. Note 217/fX is 21.8 ms during 6.0-MHz operation, and 31.3 ms during 4.19-MHz operation. 215/fX is 5.46 ms during 6.0-MHz operation, and 7.81 ms during 4.19-MHz operation. Caution Noise resistance and noise radiation are different in PROM and mask ROM versions. In transferring to mask ROM versions from the PROM version in a process between prototype development and full production, be sure to fully evaluate the mask ROM version's CS (not ES). 17 PD75P3036 6. PROGRAM COUNTER (PC) AND MEMORY MAP 6.1 Program Counter (PC) ... 14 bits This is a 14-bit binary counter that stores program memory address data. Figure 6-1. Configuration of Program Counter PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC 6.2 Program Memory (PROM) ... 16384 x 8 bits The program memory consists of 16384 x 8-bit one-time PROM or EPROM. * Addresses 0000H and 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. * Addresses 0002H to 000DH Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are written. Interrupt processing can start from any address. * Addresses 0020H to 007FH Table area referenced by the GETI instruction Note. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte/3-byte instruction, or two 1-byte instructions. It is used to decrease the number of program steps. 18 PD75P3036 Figure 6-2 shows the addressing ranges for the program memory, branch instruction and the subroutine call instruction. Figure 6-2. Program Memory Map 7 0000H MBE 6 RBE 5 0 Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) CALLF !faddr instruction entry address Branch address for the following instructions * BR BCXA * BR BCDE * BR !addr Note * BRA !addr1 * CALLA !addr1Note 0004H MBE RBE INT0 start address (upper 6 bits) INT0 start address (lower 8 bits) 0006H MBE RBE INT1 start address (upper 6 bits) INT1 start address (lower 8 bits) BRCB !caddr instruction branch address 0008H MBE RBE INTCSI start address (upper 6 bits) INTCSI start address (lower 8 bits) 000AH MBE RBE INTT0 start address (upper 6 bits) INTT0 start address (lower 8 bits) 000CH MBE RBE INTT1, INTT2 start address (upper 6 bits) INTT1, INTT2 start address (lower 8 bits) CALL !addr instruction subroutine entry address Branch/call address by GETI 0020H Reference table for GETI instruction 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH BR $addr instruction relative branch address (-15 to -1, +2 to +16) BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address * Note Can be used only in the Mk II mode. Remark For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC's lower 8 bits only. 19 PD75P3036 6.3 Data Memory (RAM) ... 768 x 4 bits Figure 6-3 shows the data memory configuration. Data memory consists of a data area and a peripheral hardware area. The data area consists of 768 x 4-bit static RAM. Figure 6-3. Data Memory Map Data memory 000H General-purpose register area 01FH 020H 0 256 x 4 (224 x 4) 0FFH 100H 256 x 4 (236 x 4) 1EBH 1ECH Display data memory 1FFH 200H Data area static RAM (768 x 4) Stack area Note 256 x 4 2 (20 x 4) 1 (32 x 4) Memory bank 2FFH Not incorporated F80H Peripheral hardware area 128 x 4 15 FFFH Note Memory bank 0, 1, or 2 can be selected as the stack area. 20 PD75P3036 7. INSTRUCTION SET (1) Representation and coding formats for operands In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's operand representations (for further description, see the RA75X Assembler Package User's Manual--Language (EEU-1363)). When there are several codes, select and use just one. Codes that consist of uppercase letters and + or - symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, see the User's Manual). The number of labels that can be entered for fmem and pmem are restricted. Representation reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IEXXX RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-3FFFH immediate data or label 0000H-3FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (however, bit0 = 0) or label PORT0-PORT8 IEBT, IECSI, IET0-IET2, IE0-IE2, IE4, IEW RB0-RB3 MB0-MB2, MB15 Coding format Note When processing 8-bit data, only even-numbered addresses can be entered. 21 PD75P3036 (2) Operation legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS IEXXX RBS MBS PCC . (XX) XXH : A register; 4-bit accumulator : B register : C register : D register : E register : H register : L register : X register : Register pair (XA); 8-bit accumulator : Register pair (BC) : Register pair (DE) : Register pair (HL) : Expansion register pair (XA') : Expansion register pair (BC') : Expansion register pair (DE') : Expansion register pair (HL') : Program counter : Stack pointer : Carry flag; bit accumulator : Program status word : Memory bank enable flag : Register bank enable flag : Interrupt master enable flag : Interrupt priority selection register : Interrupt enable flag : Register bank selection register : Memory bank selection register : Processor clock control register : Delimiter for address and bit : The contents addressed by XX : Hexadecimal data PORTn : Port n (n = 0 to 8) 22 PD75P3036 (3) Description of symbols used in addressing area MB = MBE * MBS *1 MBS = 0-2, 15 *2 MB = 0 MBE = 0 *3 MBE = 1 : MB = MBS MBS = 0-2, 15 *4 *5 *6 *7 (Current PC) +2 to (Current PC) +16 caddr = 0000H-0FFFH (PC13, 12 = 00B: Mk I or Mk II mode) or 1000H-1FFFH (PC13, 12 = 01B: Mk I or Mk II mode) or *8 2000H-2FFFH (PC13, 12 = 10B: Mk I or Mk II mode) or 3000H-3FFFH (PC13, 12 = 11B: Mk I or Mk II mode) *9 *10 *11 faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-3FFFH Program memory addressing MB = 15, fmem = FB0H-FBFH, FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3FFFH addr, addr1 = (Current PC) -15 to (Current PC) -1 : MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) Data memory addressing Remarks 1. MB indicates access-enabled memory banks. 2. In area *2, MB = 0 for both MBE and MBS. 3. In areas *4 and *5, MB = 15 for both MBE and MBS. 4. Areas *6 to *11 indicate corresponding address-enabled areas. (4) Description of machine cycles S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below. * No skip ..................................................................... S = 0 * Skipped instruction is 1-byte or 2-byte instruction .... S = 1 * Skipped instruction is 3-byte instruction Note .............. S = 2 Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1 Caution The GETI instruction is skipped for one machine cycle. One machine cycle equals one cycle (= tCY) of the CPU clock . Use the PCC setting to select among four cycle times. 23 PD75P3036 Instruction group Transfer Mnemonic MOV Operand A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg1 XA, rp' reg1, A rp'1, XA No. of Machine bytes cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 A<-n4 reg1<-n4 XA<-n8 HL<-n8 rp2<-n8 A<-(HL) Operation Addressing area Skip condition String-effect A String-effect A String-effect B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L=FH A<-(HL), then L<-L+1 A<-(HL), then L<-L-1 A<-(rpa1) XA<-(HL) (HL)<-A (HL)<-XA A<-(mem) XA<-(mem) (mem)<-A (mem)<-XA A<-reg1 XA<-rp' reg1<-A rp'1<-XA A<->(HL) A<->(HL), then L<-L+1 A<->(HL), then L<-L-1 A<->(rpa1) XA<->(HL) A<->(mem) XA<->(mem) A<->reg1 XA<->rp' XA<-(PC13-8+DE)ROM XA<-(PC13-8+XA)ROM XA<-(BCDE)ROM Note XA<-(BCXA)ROM Note XCH A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL A, mem XA, mem A, reg1 XA, rp' *1 *1 *1 *2 *1 *3 *3 L=0 L=FH Table reference MOVT XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA *6 *6 Note Only the lower 2 bits in the B register are valid. 24 PD75P3036 Instruction group Bit transfer Mnemonic MOV1 Operand CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY No. of Machine bytes cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1 1 2 2 1 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S Operation CY<-(fmem.bit) CY<-(pmem7-2+L3-2.bit(L1-0)) CY<-(H+mem3-0.bit) (fmem.bit)<-CY (pmem7-2+L3-2.bit(L1-0))<-CY (H+mem3-0.bit)<-CY A<-A+n4 XA<-XA+n8 A<-A+(HL) XA<-XA+rp' rp'1<-rp'1+XA A, CY<-A+(HL)+CY XA, CY<-XA+rp'+CY rp'1, CY<-rp'1+XA+CY A<-A-(HL) XA<-XA-rp' rp'1<-rp'1-XA A, CY<-A-(HL)-CY XA, CY<-XA-rp'-CY rp'1, CY<-rp'1-XA-CY A<-A^n4 A<-A^(HL) XA<-XA ^rp' rp'1<-rp'1^XA A<-Avn4 A<-Av(HL) XA<-XAvrp' rp'1<-rp'1vXA A<-Avn4 A<-Av(HL) XA<-XAvrp' rp'1<-rp'1vXA CY<-A0, A3<-CY, An-1<-An A<-A reg<-reg+1 rp1<-rp1+1 (HL)<-(HL)+1 (mem)<-(mem)+1 reg<-reg-1 rp'<-rp'-1 Addressing area *4 *5 *1 *4 *5 *1 Skip condition Arithmetic/ logical operation ADDS A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA carry carry *1 carry carry carry *1 ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA *1 borrow borrow borrow SUBC A, @HL XA, rp' rp'1, XA *1 AND A, #n4 A, @HL XA, rp' rp'1, XA *1 OR A, #n4 A, @HL XA, rp' rp'1, XA *1 XOR A, #n4 A, @HL XA, rp' rp'1, XA *1 Accumulator manipulation Increment/ decrement RORC NOT INCS A A reg rp1 @HL mem reg=0 rp1=00H *1 *3 (HL)=0 (mem)=0 reg=FH rp'=FFH DECS reg rp' 25 PD75P3036 Instruction group Comparison Mnemonic SKE Operand reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' No. of Machine bytes cycle 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 Skip if reg=n4 Skip if(HL)=n4 Skip if A=(HL) Operation Addressing area Skip condition reg=n4 *1 *1 *1 (HL)=n4 A=(HL) XA=(HL) A=reg XA=rp' Skip if XA=(HL) Skip if A=reg Skip if XA=rp' CY<-1 CY<-0 Skip if CY=1 CY<-CY (mem.bit)<-1 (fmem.bit)<-1 (pmem7-2+L3-2.bit(L1-0))<-1 (H+mem3-0.bit)<-1 (mem.bit)<-0 (fmem.bit)<-0 (pmem7-2+L3-2.bit(L1-0))<-0 (H+mem3-0.bit)<-0 Skip if(mem.bit)=1 Skip if(fmem.bit)=1 Skip if(pmem7-2+L3-2.bit(L1-0))=1 Skip if(H+mem3-0.bit)=1 Skip if(mem.bit)=0 Skip if(fmem.bit)=0 Skip if(pmem7-2+L3-2.bit(L1-0))=0 Skip if(H+mem3-0.bit)=0 Skip if(fmem.bit)=1 and clear Skip if(pmem7-2+L3-2.bit (L1-0))=1 and clear Skip if(H+mem3-0.bit)=1 and clear CY<-CY^(fmem.bit) CY<-CY^(pmem7-2+L3-2.bit(L1-0)) CY<-CY^(H+mem3-0.bit) CY<-CYv(fmem.bit) CY<-CYv(pmem7-2+L3-2.bit(L1-0)) CY<-CYv(H+mem3-0.bit) CY<-CYv (fmem.bit) CY<- CYv(pmem7-2+L3-2.bit(L1-0)) CY<-CYv(H+mem3-0.bit) Carry flag manipulation SET1 CLR1 SKT NOT1 CY CY CY CY mem.bit fmem.bit pmem.@L @H+mem.bit CY=1 Memory bit manipulation SET1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 (mem.bit)=1 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 (mem.bit)=0 (fmem.bit)=0 (pmem.@L)=0 (@H+mem.bit)=0 (fmem.bit)=1 (pmem.@L)=1 (@H+mem.bit)=1 CLR1 mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit OR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit XOR1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit 26 PD75P3036 Instruction group Branch Mnemonic BRNote 1 Operand addr No. of Machine bytes cycle -- -- Operation PC13-0<-addr Use the assembler to select the most appropriate instruction among the following. * BR !addr * BRCB !caddr * BR $addr PC13-0<-addr1 Use the assembler to select the most appropriate instruction among the following. * BRA !addr1 * BR !addr * BRCB !caddr * BR $addr1 PC13-0<-addr PC13-0<-addr PC13-0<-addr1 PC13-0<-PC13-8+DE PC13-0<-PC13-8+XA PC13-0<-BCDE Note 2 PC13-0<-BCXA PC13-0<-addr1 PC13-0<-PC13, 12+caddr11-0 Note 2 Addressing area *6 Skip condition addr1 -- -- *11 !addr $addr $addr1 PCDE PCXA BCDE BCXA BRA Note 1 3 1 1 2 2 2 2 3 2 3 2 2 3 3 3 3 3 2 *6 *7 *6 *6 *11 *8 !addr1 !caddr BRCB Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. Only the lower 2 bits in the B register are valid. 27 PD75P3036 Instruction group Subroutine stack control Mnemonic CALLANote Operand !addr1 No. of Machine bytes cycle 3 3 Operation (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-5)<-0, 0, PC13, 12 (SP-2)<-X, X, MBE, RBE PC13-0<-addr1, SP<-SP-6 Addressing area *11 Skip condition CALLNote !addr 3 3 (SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12 PC13-0<-addr, SP<-SP-4 *6 4 (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-5)<-0, 0, PC13, 12 (SP-2)<-X, X, MBE, RBE PC13-0<-addr, SP<-SP-6 CALLFNote !faddr 2 2 (SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12 PC13-0<-000+faddr, SP<-SP-4 *9 3 (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-5)<-0, 0, PC13, 12 (SP-2)<-X, X, MBE, RBE PC13-0<-000+faddr, SP<-SP-6 RET Note 1 3 MBE, RBE, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) SP<-SP+4 X, X, MBE, RBE<-(SP+4) PC11-0<-(SP)(SP+3)(SP+2) 0, 0, PC13, 12<-(SP+1) SP<-SP+6 RETSNote 1 3+S MBE, RBE, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) SP<-SP+4 then skip unconditionally X, X, MBE, RBE<-(SP+4) PC11-0<-(SP)(SP+3)(SP+2) 0, 0, PC13, 12<-(SP+1) SP<-SP+6 then skip unconditionally Unconditional RETI Note 1 3 MBE, RBE, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) PSW<-(SP+4)(SP+5), SP<-SP+6 0, 0, PC13, 12<-(SP+1) PC11-0<-(SP)(SP+3)(SP+2) PSW<-(SP+4)(SP+5), SP<-SP+6 Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 28 PD75P3036 Instruction group Subroutine stack control Mnemonic PUSH rp BS POP rp BS Operand No. of Machine bytes cycle 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 Operation (SP-1)(SP-2)<-rp, SP<-SP-2 (SP-1)<-MBS, (SP-2)<-RBS, SP<-SP-2 rp<-(SP+1)(SP), SP<-SP+2 MBS<-(SP+1), RBS<-(SP), SP<-SP+2 IME(IPS.3)<-1 IEXXX<-1 IME(IPS.3)<-0 IEXXX<-0 A<-PORTn (n=0-8) Addressing area Skip condition Interrupt control EI IEXXX DI IEXXX 2 2 2 2 2 2 2 2 2 1 I/O IN Note 1 A, PORTn XA, PORTn XA<-PORTn+1, PORTn (n=4, 6) PORTn<-A (n=2-8) OUTNote 1 PORTn, A PORTn, XA PORTn+1, PORTn<-XA (n=4, 6) Set HALT Mode(PCC.2<-1) Set STOP Mode(PCC.3<-1) No Operation RBS<-n (n=0-3) MBS<-n (n=0-2, 15) * When using TBR instruction PC13-0<-(taddr)5-0+(taddr+1) -------------------------------------- CPU control HALT STOP NOP *10 Special SEL RBn MBn 2 2 1 GETI Note 2, 3 taddr * When using TCALL instruction (SP-4)(SP-1)(SP-2)<-PC11-0 (SP-3)<-MBE, RBE, PC13, 12 PC13-0<-(taddr)5-0+(taddr+1) SP<-SP-4 -------------------------------------- * When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instruction 1 3 * When using TBR instruction PC13-0<-(taddr)5-0+(taddr+1) -------------------------------- Determined by referenced instruction *10 ------------ 4 * When using TCALL instruction (SP-6)(SP-3)(SP-4)<-PC11-0 (SP-5)<-MBE, RBE, PC13, 12 (SP-2)<-X, X, MBE, RBE PC13-0<-(taddr)5-0+(taddr+1) SP<-SP-6 -------------------------------- ------------ 3 * When using instruction other than TBR or TCALL Execute (taddr)(taddr+1) instruction Determined by referenced instruction Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15. 2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction's table definitions. 3. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 29 PD75P3036 8. PROM (PROGRAM MEMORY) WRITE AND VERIFY The PD75P3036 contains a 16384 x 8-bit PROM as a program memory. The pins listed in the table below are used for this PROM's write/verify operations. Clock input from the X1 pin is used instead of address input as a method for updating addresses. Pin VPP X1, X2 Function Pin where program voltage is applied during program memory write/verify (usually VDD potential) Clock input pins for address updating during program memory write/verify. Input the X1 pin's inverted signal to the X2 pin. Operation mode selection pin for program memory write/verify 8-bit data I/O pins for program memory write/verify MD0 to MD3 D0/P40 to D3/P43 (lower 4 bits) D4/P50 to D7/P53 (upper 4 bits) VDD Pin where power supply voltage is applied. Applies 1.8 to 5.5 V in normal operation mode and +6 V for program memory write/verify. Caution Pins not used for program memory write/verify should be connected to VSS. 8.1 Operation Modes for Program Memory Write/Verify When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the PD75P3036 enters the program memory write/verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below. Operation mode specification VPP +12.5 V VDD +6 V MD0 H L L H MD1 L H L X MD2 H H H H MD3 L H H H Zero-clear program memory address Write mode Verify mode Program inhibit mode Operation mode X: L or H 30 PD75P3036 * 8.2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull unused pins to VSS through resistors. Set the X1 pin low. Supply 5 V to the VDD and VPP pins. Wait 10 s. Select the zero-clear program memory address mode. Supply 6 V to the VDD and 12.5 V to the VPP pins. Write data in the 1 ms write mode. Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7). (X : number of write operations from steps (6) and (7)) x 1 ms additional write. Apply four pulses to the X1 pin to increment the program memory address by one. (10) Repeat steps (6) to (9) until the end address is reached. (11) Select the zero-clear program memory address mode. (12) Return the VDD and VPP pins back to 5 V. (13) Turn off the power. The following figure shows steps (2) to (9). X repetitions Write Verify Additional write Address increment VPP VPP VDD VDD + 1 VDD VDD X1 D0/P40-D3/P43 D4/P50-D7/P53 Data input Data output Data input MD0/P30 MD1/P31 MD2/P32 MD3/P33 31 PD75P3036 * 8.3 Program Memory Read Procedure The PD75P3036 can read program memory contents using the following procedure. (1) (2) (3) (4) (5) (6) (7) (8) (9) Pull unused pins to VSS through resistors. Set the X1 pin low. Supply 5 V to the VDD and VPP pins. Wait 10 s. Select the zero-clear program memory address mode. Supply 6 V to the VDD and 12.5 V to the VPP pins. Select the verify mode. Apply four clock pulses to the X1 pin. Every four clock pulses will output the data stored in one address. Select the zero-clear program memory address mode. Return the VDD and VPP pins back to 5 V. Turn off the power. The following figure shows steps (2) to (7). VPP VPP VDD VDD + 1 VDD VDD X1 D0/P40-D3/P43 D4/P50-D7/P53 Data output Data output MD0/P30 MD1/P31 "L" MD2/P32 MD3/P33 32 PD75P3036 * 9. PROGRAM ERASURE (PD75P3036KK-T ONLY) The PD75P3036KK-T is capable of erasing (FFH) the data written in a program memory and rewriting. To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm. Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase the programmed data is as follows: * UV intensity x erasure time : 15 W* s/cm2 or more * Erasure time : 15 to 20 minutes (when a UV lamp of 12000 W/cm2 is used. However, a longer time may be needed because of deterioration in performance of the UV lamp, soiled erasure window, etc.) When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a filter is provided for a UV lamp, irrradiate the ultraviolet rays after removing the filter. * 10. OPAQUE FILM ON ERASURE WINDOW (PD75P3036KK-T ONLY) To protect from unintentional erasure by rays other than that of the lamp for erasing EPROM contents, and to protect internal circuit other than EPROM from misoperating due to light radiation, cover the erasure window with an opaque film when EPROM contents erasure is not performed. 11. ONE-TIME PROM SCREENING Due to its structure, the one-time PROM versions (PD75P3036GC-3B9, PD75P3036GK-BE9) cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening. Storage temperature 125 C Storage time 24 hours 33 PD75P3036 * 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 C) Parameter Supply voltage PROM supply voltage Input voltage Symbol VDD VPP VI1 VI2 Output voltage High-level output current VO IOH Per pin Total of all pins Low-level output current IOL Per pin Total of all pins Operating ambient temperature Storage temperature TA Tstg Other than ports 4, 5 Ports 4, 5 N-ch open drain Conditions Ratings -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD +0.3 -0.3 to +14 -0.3 to VDD +0.3 -10 -30 30 200 -40 to +85 Note -65 to +150 Unit V V V V V mA mA mA mA C C Note To drive LCD at 1.8 V VDD < 2.7 V, TA = -10 to +85 C Caution If the absolute maximum ratings of even one of the parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded when using the product. Capacitance (TA = 25 C, VDD = 0 V) Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF 34 PD75P3036 Main System Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Recommended Constants Resonator Ceramic resonator Parameter Oscillation frequency (fX) Note 1 Conditions MIN. 1.0 TYP. MAX. Unit 6.0 Note 2 MHz X1 X2 C1 VDD Crystal resonator X1 X2 C2 Oscillation stabilization timeNote 3 After VDD has reached MIN. value of oscillation voltage range 1.0 4 ms Oscillation frequency (fX) Note 1 6.0 Note 2 MHz C1 VDD External clock X1 X2 C2 Oscillation stabilization timeNote 3 VDD = 4.5 to 5.5 V 10 30 ms X1 input frequency (fX) Note 1 1.0 6.0 Note 2 MHz X1 input high-, low-level widths (tXH, tXL) 83.3 500 ns Notes 1. 2. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, do not select the processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle time is less than 0.95 s, falling short of the rated value of 0.95 s. 3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. Caution When using the main system clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillation circuit. 35 PD75P3036 Subsystem Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Recommended Constants Resonator Crystal resonator Parameter Oscillation frequency (fXT) Note 1 Conditions MIN. 32 TYP. 32.768 MAX. 35 Unit kHz XT1 XT2 R C3 VDD External clock XT1 XT2 C4 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V 1.0 2 10 s XT1 input frequency (fXT) Note 1 32 100 kHz XT1 input high-, low-level widths (tXTH, tXTL) 5 15 s Notes 1. 2. The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the instruction execution time, refer to AC Characteristics. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring in the vicinity of a line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VDD. * Do not ground to a power supply pattern through which a high current flows. * Do not extract signals from the oscillation circuit. The subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit. 36 PD75P3036 DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter Low-level output current High-level input voltage VIH2 Ports 0, 1, 6, 7, P80, P81, RESET VIH3 Ports 4, 5 N-ch open drain VIH1 Symbol IOL Per pin Total of all pins Ports 2, 3, P82, P83 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VIH4 Low-level input voltage VIL2 Ports 0, 1, 6, 7, P80, P81, RESET VIL3 High-level output voltage Low-level output voltage VOL1 VOH X1, XT1 SCK, SO, ports 2, 3, 6, 7, 8, BP0 to BP7 IOH = -1 mA SCK, SO, ports 2 to 8, BP0 to BP7 IOL = 15 mA VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 N-ch open drain Pull-up resistor 1 k High-level input leakage current ILIH1 ILIH2 ILIH3 Low-level input leakage current ILIL1 ILIL2 VIN = 13 V VIN = 0 V VIN = VDD Pins other than X1, XT1 X1, XT1 Ports 4, 5 (N-ch open drain) Pins other than ports 4, 5, X1, XT1 X1, XT1 Ports 4, 5 (N-ch open drain) When input instruction is not executed ILIL3 Ports 4, 5 (N-ch open drain) When input instruction is executed VOUT = VDD -30 VDD = 5 V VDD = 3 V -10 -3 -27 -8 3 3 20 20 -3 -20 -3 0.4 0.2 VDD V V 0.2 2.0 V VIL1 X1, XT1 Ports 2, 3, 4, 5, P82, P83 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V 0.7 VDD 0.9 VDD 0.8 VDD 0.9 VDD 0.7 VDD 0.9 VDD VDD-0.1 0 0 0 0 0 VDD-0.5 Conditions MIN. TYP. MAX. 15 120 VDD VDD VDD VDD 13 13 VDD 0.3 VDD 0.1 VDD 0.2 VDD 0.1 VDD 0.1 Unit mA mA V V V V V V V V V V V V V A A A A A A A A A A A A k High-level output leakage current ILOH1 SCK, SO/SB0, SB1, ports 2, 3, 6, 7, 8, BP0 to BP7 ILOH2 Low-level output leakage current Internal pull-up resistor RL1 ILOL VOUT = 13 V Ports 4, 5 (N-ch open drain) VOUT = 0 V 20 -3 VIN = 0 V Ports 0 to 3, 6 to 8 (except pin P00) 50 100 200 37 PD75P3036 DC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter LCD drive voltage Symbol VLCD VAC0 = 0 Conditions -40 to + 85 C -10 to + 85 C VAC0 = 1 VAC current Note 1 LCD output voltage deviationNote 2 (common) LCD output voltage deviationNote 2 (segment) Supply currentNotes 1, 3 IDD1 6.00 MHz Note 4 crystal oscillation C1 = C2 = 22 pF 4.19 MHz Note 4 MIN. 2.7 2.2 1.8 TYP. MAX. VDD VDD VDD Unit V V V IVAC VODC VAC0 = 1, VDD = 2.0 V 10 % IO = 1.0 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 0 1 4 0.2 A V VODS IO = 0.5 A 1.8 V VLCD VDDNote 1 0 0.2 V VDD = 5.0 V 10 % Note 5 VDD = 3.0 V 10 % Note 6 HALT mode VDD = 5.0 V 10 % VDD = 3.0 V 10 % % Note 5 3.5 0.86 0.9 0.5 2.7 0.33 0.7 0.3 45 22 45 43 43 8.5 3.0 8.5 4.6 4.6 0.05 0.02 10.5 2.5 2.7 1.0 8.1 1.0 2.0 0.9 135 66 90 129 86 25 9.0 17 13.8 9.2 10 5.0 3.0 mA mA mA mA mA mA mA mA IDD2 IDD1 VDD = 5.0 V 10 HALT mode Lowvoltage mode Note 8 IDD2 crystal oscillation C1 = C2 = 22 pF VDD = 3.0 V 10 % Note 6 VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 3.0 V 10 % VDD = 2.0 V 10 % VDD = 3.0 V, TA = 25 C VDD = 3.0 V 10 % VDD = 3.0 V, TA = 25 C Lowvoltage VDD = 3.0 V 10 % VDD = 2.0 V 10 % IDD3 32.768 kHz Note 7 crystal oscillation A A A A A A A A A A A A A Low current dissipation mode Note 9 IDD4 HALT mode mode Note 8 VDD = 3.0 V, TA = 25 C Low current dissipation VDD = 3.0 V 10 % mode Note 9 VDD = 3.0 V, TA = 25 C IDD5 XT1 = 0V Note 10 VDD = 5.0 V 10 % VDD = 3.0 V 10 % TA = 25 C STOP mode 0.02 Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. Clear VAC0 to 0 in the low current dissipation mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 A. Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and common outputs and the output voltage. The current flowing through the internal pull-up resistor is not included. Including the case when the subsystem clock oscillates. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. When the device operates in low-speed mode with PCC set to 0000. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. When the sub-oscillation circuit control register (SOS) is set to 0000. When SOS is set to 0010. care). 10. When SOS is set to 00x1, and the feedback resistor of the sub-oscillation circuit is not used (x : don't 38 PD75P3036 AC Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter CPU clock cycle timeNote 1 tCY Symbol Operates with main system clock Operates with subsystem clock Conditions VDD = 2.7 to 5.5 V MIN. 0.67 0.95 114 TYP. MAX. 64 64 Unit s s s MHz kHz (minimum instruction execution time = 1 machine cycle) TI0, TI1, TI2 input frequency fTI 122 125 VDD = 2.7 to 5.5 V 0 0 1.0 275 TI0, TI1, TI2 high-, low-level widths Interrupt input high-, low-level widths tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 1.8 s s s s s s s tINTH, tINTL INT0 IM02 = 0 IM02 = 1 Note 2 10 10 10 10 tCY vs VDD INT1, 2, 4 KR0 to KR7 RESET low-level width tRSL Notes 1. The cycle time of the CPU clock () is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock. Cycle time tCY [ s] 64 60 6 5 (with main system clock) Operation guaranteed range 4 3 2. 2tCY or 128/fX depending on the setting of the interrupt mode register (IM0). 2 1 0.5 0 1 2 3 4 5 6 Supply voltage VDD [V] 39 PD75P3036 Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK *** internal clock output): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY1 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths SINote 1 setup time (to SCK ) tKL1, tKH1 tSIK1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V tKCY1/2-50 tKCY1/2-150 150 500 SINote 1 hold time (from SCK ) SCK SONote 1 output delay time tKSO1 RL = 1 k, Note 2 TYP. MAX. Unit ns ns ns ns ns ns ns ns tKSI1 VDD = 2.7 to 5.5 V 400 600 VDD = 2.7 to 5.5 V 0 0 250 1000 ns ns CL = 100 pF Notes 1. 2. Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 2-wire and 3-wire serial I/O modes (SCK *** external clock input): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY2 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths SINote 1 setup time (to SCK ) SINote 1 hold time (from SCK ) SCK SONote 1 output delay time tKSO2 RL = 1 k, Note 2 TYP. MAX. Unit ns ns ns ns ns ns ns ns tKL2, tKH2 tSIK2 VDD = 2.7 to 5.5 V 400 1600 VDD = 2.7 to 5.5 V 100 150 tKSI2 VDD = 2.7 to 5.5 V 400 600 VDD = 2.7 to 5.5 V 0 0 300 1000 ns ns CL = 100 pF Notes 1. 2. Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 40 PD75P3036 SBI mode (SCK *** internal clock output (master)): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY3 Conditions VDD = 2.7 to 5.5 V MIN. 1300 3800 SCK high-, low-level widths tKL3, tKH3 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI3 tKSO3 RL = 1 k, CL = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns ns VDD = 2.7 to 5.5 V tKCY3/2-50 tKCY3/2-150 tSIK3 VDD = 2.7 to 5.5 V 150 500 tKCY3/2 VDD = 2.7 to 5.5 V 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line. SBI mode (SCK *** external clock input (slave)): (TA = -40 to +85 C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKCY4 Conditions VDD = 2.7 to 5.5 V MIN. 800 3200 SCK high-, low-level widths tKL4, tKH4 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SCK SB0, 1 output delay time SCK SB0, 1 SB0, 1 SCK SB0, 1 low-level width SB0, 1 high-level width tKSB tSBK tSBL tSBH tKSI4 tKSO4 RL = 1 k, CL = 100 pF Note TYP. MAX. Unit ns ns ns ns ns ns ns VDD = 2.7 to 5.5 V 400 1600 tSIK4 VDD = 2.7 to 5.5 V 100 150 tKCY4/2 VDD = 2.7 to 5.5 V 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns Note RL and CL respectively indicate the load resistance and load capacitance of the SB0, 1 output line. 41 PD75P3036 A/D Converter Characteristics (TA = -40 to +85 C, VDD = 1.8 to 5.5 V, 1.8 V AVREF VDD) Parameter Resolution Absolute accuracy Note 1 Symbol Conditions 2.7 V VDD 5.5 V 1.8 V VDD < 2.7 V VDD AVREF MIN. 8 TYP. 8 MAX. 8 1.5 3 3 168/fX 44/fX Unit bit LSB LSB LSB VDD = AVREF Conversion time Sampling time Analog input voltage Analog input impedance AVREF current tCONV tSAMP VIAN RAN IREF Note 2 Note 3 AVSS 1000 0.25 s s V M AVREF 2.0 mA Notes 1. 2. 3. Absolute accuracy excluding quantization error (1/2LSB) Time until end of conversion (EOC = 1) after execution of conversion start instruction (40.1 s: fX = 4.19 MHz). Time until end of sampling after execution of conversion start instruction (10.5 s: fX = 4.19 MHz). 42 PD75P3036 AC timing test points (except X1 and XT1 inputs) VIH (MIN.) VIL (MAX.) VIH (MIN.) VIL (MAX.) VOH (MIN.) VOL (MAX.) VOH (MIN.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD - 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD - 0.1 V XT1 input 0.1 V TI0, TI1, TI2 timing 1/fTI tTIL tTIH TI0, TI1, TI2 43 PD75P3036 Serial transfer timing 3-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SI Input data tKSO1, 2 SO Output data 2-wire serial I/O mode tKCY1, 2 tKL1, 2 tKH1, 2 SCK tSIK1, 2 tKSI1, 2 SB0, 1 tKSO1, 2 44 PD75P3036 Serial transfer timing Bus release signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSBK tSIK3, 4 tKSI3, 4 SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 SCK tKSB tSBK tSIK3, 4 tKSI3, 4 tKH3, 4 SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET input timing tRSL RESET 45 PD75P3036 Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = -40 to +85 C) Parameter Release signal setup time Oscillation stabilization wait time Note 1 Symbol tSREL tWAIT Released by RESET Released by interrupt request Conditions MIN. 0 2 15/fX Note 2 TYP. MAX. Unit s ms ms Notes 1. 2. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. Set by the basic interval timer mode register (BTM). (Refer to the table below.) Wait Time fX = 4.19 MHz - - - - 0 0 1 1 0 1 0 1 0 1 1 1 2 20/fX (approx. 250 ms) 2 17/fX (approx. 31.3 ms) 2 15/fX (approx. 7.81 ms) 2 13/fX (approx. 1.95 ms) fX = 6.0 MHz 2 20/fX (approx. 175 ms) 2 17/fX (approx. 21.8 ms) 2 15/fX (approx. 5.46 ms) 2 13/fX (approx. 1.37 ms) BTM3 BTM2 BTM1 BTM0 Data retention timing (when STOP mode released by RESET) Internal reset operation Oscillation stabilization wait time STOP mode Data retention mode Operation mode VDD STOP instruction execution VDDDR tSREL RESET tWAIT Data retention timing (standby release signal: when STOP mode released by interrupt signal) Oscillation stabilization wait time STOP mode Data retention mode Operation mode VDD STOP instruction execution Standby release signal (interrupt request) VDDDR tSREL tWAIT 46 PD75P3036 DC Programming Characteristics (TA = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter High-level input voltage Symbol VIH1 VIH2 Low-level input voltage VIL1 VIL2 Input leakage current High-level output voltage Low-level output voltage VDD supply current VPP supply current ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Except X1, X2 X1, X2 Except X1, X2 X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD-1.0 0.4 30 30 Conditions MIN. 0.7 VDD VDD-0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V A V V mA mA Cautions 1. 2. Ensure that VPP does not exceed +13.5 V including overshoot. VDD must be applied before VPP, and cut after VPP. AC Programming Characteristics (TA = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) Parameter Address setup time Note 2 Symbol (to MD0) tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tM0S tDV tM1H tM1R tPCR tXH, tXL fX tI tM3S tM3H tM3SR Note 1 tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR -- -- -- -- -- -- -- tACC tOH -- -- Conditions MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2 TYP. MAX. Unit s s s s s 130 ns MD1 setup time (to MD0) Data setup time (to MD0) Address hold time Note 2 (from MD0) Data hold time (from MD0) MD0Data output float delay time VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width Additional program pulse width MD0 setup time (to MD1) MD0Data output delay time MD1 hold time (from MD0) MD1 recovery time (from MD0) Program counter reset time X1 input high-, low-level widths X1 input frequency Initial mode setting time MD3 setup time (to MD1) MD3 hold time (from MD1) MD3 setup time (to MD0) s s 1.0 1.05 21.0 ms ms s 1 MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125 s s s s s 4.19 2 2 2 Program memory read Program memory read Program memory read Program memory read Program memory read 0 2 2 2 2 130 MHz s s s s s s s s Data output delay time from address Note 2 tDAD Data output hold time from address MD3 hold time (from MD0) MD3Data output float delay time Note 2 tHAD tM3HR tDFR Notes 1. 2. Symbol of corresponding PD27C256A The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin. 47 PD75P3036 Program Memory Write Timing tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL Data Input tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tM0S tOPW tDS tDH tDV tDF Data Output Data Input tDS tDH tAH tAS Data Input tXH D0/P40-D3/P43 D4/P50-D7/P53 Program Memory Read Timing tVPS VPP VPP VDD tVDS VDD+1 VDD VDD X1 tXL tHAD D0/P40-D3/P43 D4/P50-D7/P53 tI MD0 tDV tM3HR Data Output Data Output tDFR tDAD tXH MD1 tPCR MD2 tM3SR MD3 48 PD75P3036 * 13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) IDD vs. VDD (main system clock: 6.0-MHz crystal resonator) (TA = 25 C ) 10 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT mode + 32 kHz oscillation 1.0 0.5 Supply current IDD (mA) 0.1 Subsystem clock operation mode (SOS.1 = 0) 0.05 Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 0) Subsystem clock HALT mode (SOS.1 = 1) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 1) 0.01 0.005 X1 X2 XT1 XT2 Crystal resonator Crystal resonator 6.0 MHz 32.768 kHz 330 k 22 pF 22 pF VDD 22 pF VDD 22 pF 0.001 0 1 2 3 4 Supply voltage VDD (V) 5 6 7 8 49 PD75P3036 IDD vs. VDD (main system clock: 4.19-MHz crystal resonator) 10 (TA = 25 C) 5.0 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 1.0 Main system clock HALT mode + 32 kHz oscillation 0.5 Supply current IDD (mA) 0.1 Subsystem clock operation mode (SOS.1 = 0) 0.05 Subsystem clock HALT mode (SOS.1 = 0) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 0) 0.01 Subsystem clock HALT mode (SOS.1 = 1) Main system clock STOP mode + 32 kHz oscillation (SOS.1 = 1) 0.005 X1 X2 XT1 XT2 Crystal resonator Crystal resonator 4.19 MHz 32.768 kHz 330 k 22 pF 22 pF VDD 22 pF VDD 22 pF 0.001 0 1 2 3 4 Supply voltage VDD (V) 5 6 7 8 50 PD75P3036 14. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x14) A B 60 61 41 40 detail of lead end CD S Q R 80 1 21 20 F G H P I M J K M N L NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 17.20.4 14.00.2 14.00.2 17.20.4 0.825 0.825 0.300.10 0.13 0.65 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.10.1 55 3.0 MAX. INCHES 0.6770.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0040.004 55 0.119 MAX. S80GC-65-3B9-4 51 PD75P3036 80 PIN PLASTIC TQFP (FINE PITCH) ( A B 12) 60 61 41 40 detail of lead end C D S Q 80 21 1 20 F G H I M J K P N L NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B C D F G H I J K L M N P Q R S 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 M 0.145 +0.055 0.0060.002 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4 52 R PD75P3036 * 80 PIN CERAMIC WQFN A B K Q T U1 C D W 80 H IM J 1 R S U Z X80KW-65A-1 NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K Q R S T U U1 W Z MILLIMETERS 14.0 0.2 13.6 13.6 14.0 0.2 1.84 3.6 MAX. 0.45 0.10 0.06 0.65 (T.P.) 1.0 0.15 C 0.3 0.825 0.825 R 2.0 9.0 2.1 0.75 0.15 0.10 INCHES 0.551 0.008 0.535 0.535 0.551 0.008 0.072 0.142 MAX. 0.018+0.004 -0.005 0.003 0.024 (T.P.) 0.039+0.007 -0.006 C 0.012 0.032 0.032 R 0.079 0.354 0.083 0.030+0.006 -0.007 0.004 F G 53 PD75P3036 * 15. RECOMMENDED SOLDERING CONDITIONS Solder the PD75P3036 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For the soldering methods and conditions other than those recommended, consult NEC. Table 15-1. Soldering Conditions of Surface Mount Type (1) PD75P3036GC-3B9: 80-pin plastic QFP (14 x 14 mm) Soldering Method Infrared reflow VPS Wave soldering Soldering Conditions Package peak temperature: 235 C, Reflow time: 30 seconds or below (210 C or higher), Number of reflow processes: 3 max. Package peak temperature: 215 C, Reflow time: 40 seconds or below (200 C or higher), Number of reflow processes: 3 max. Solder temperature: 260 C or below, Flow time: 10 seconds or below, Number of flow processes: 1 Preheating temperature: 120 C or below (package surface temperature) Pin temperature: 300 C or below, Time: 3 seconds or below (per side of device) Symbol IR35-00-3 VP15-00-3 WS60-00-1 Pin partial heating -- Caution Do not use two or more soldering methods in combination (except the pin partial heating method). (2) PD75P3036GK-BE9: 80-pin plastic TQFP (fine pitch) (12 x 12 mm) Soldering Method Infrared reflow Soldering Conditions Symbol Package peak temperature: 235 C, Reflow time: 30 seconds or below (210 C IR35-107-3 or higher), Number of reflow processes: 3 max., Exposure limit: 7 days Note (After that, prebaking is necessary at 125 C for 10 hours.) Package peak temperature: 215 C, Reflow time: 40 seconds or below (200 C VP15-107-3 or higher), Number of reflow processes: 3 max., Exposure limit: 7 days Note (After that, prebaking is necessary at 125 C for 10 hours.) Solder temperature: 260 C or below, Flow time: 10 seconds or below, WS60-107-1 Number of flow processes: 1, Preheating temperature: 120 C or below (package surface temperature) Exposure limit: 7 days Note (After that, prebaking is necessary at 125 C for 10 hours.) Pin temperature: 300 C or below, Time: 3 seconds or below (per side of device) -- VPS Wave soldering Pin partial heating Note The number of days for storage after the dry pack has been opened. The storage conditions are 25 C, 65 % RH max. Caution Do not use two or more soldering methods in combination (except the pin partial heating method). 54 PD75P3036 APPENDIX A. FUNCTION LIST OF PD75336, 753036, AND 75P3036 PD75336 ROM (bytes) RAM (x 4 bits) Mk I, Mk II mode selection function Instruction set I/O ports Total CMOS input CMOS I/O CMOS output N-ch open-drain I/O Mask options Timers 16256 Mask ROM 768 No 75X High-End 44 8 20 (4 of which can directly drive LEDs) 8 (also used as segment pins) 8 (can directly drive LEDs, medium-voltage port) Yes 4 channels: * 8-bit timer/ event counter ........ 2 chs * Basic interval timer ... 1 ch * Watch timer .......... 1 ch * External : 3 * Internal : 4 * External : 1 * Internal : 1 VDD = 2.7 to 6.0 V 0.95, 1.91, 3.81, or 15.3 s (@ 4.19 MHz) 122 s (@ 32.768 kHz) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin plastic QFP (14 x 14 mm) 80-pin plastic TQFP (fine pitch) (12 x 12 mm) 80-pin ceramic WQFN No 5 channels: * 8-bit timer/event counters ........................ 3 chs (16-bit timer/event counter, carrier generator, timer with gate) * Basic interval timer/watchdog timer ......... 1 ch * Watch timer ............................................. 1 ch * External : 3 * Internal : 5 * External : 1 * Internal : 1 VDD = 1.8 to 5.5 V * 0.95, 1.91, 3.81, or 15.3 s (@ 4.19 MHz) * 0.67, 1.33, 2.67, or 10.7 s (@ 6.0 MHz) Yes 75XL PD753036 16384 Mask ROM PD75P3036 16384 One-time PROM, EPROM Vectored interrupt Test input Power supply voltage Instruction execution time When main system clock is selected When subsystem clock is selected Package 55 PD75P3036 APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the PD75P3036. Use the common relocatable assembler for the series together with the device file according to the model. RA75X relocatable assembler Host machine OS PC-9800 Series MS-DOS TM Part No. (name) Supply medium 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HC 5-inch 2HC S5A13RA75X S5A10RA75X S7B13RA75X S7B10RA75X * Device file Ver.3.30 to Ver.6.2Note IBM PC/ATTM or compatible Refer to "OS for IBM PCs" Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note IBM PC/AT or compatible Refer to "OS for IBM PCs" Supply medium 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HC 5-inch 2HC Part No. (name) S5A13DF753036 S5A10DF753036 S7B13DF753036 S7B10DF753036 * Remark Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Operations of the assembler and device file are guaranteed only when using the host machine and OS described above. 56 PD75P3036 PROM Write Tools Hardware PG-1500 This is a PROM programmer that can program single-chip microcontroller with PROM in stand alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities ranging from 256 K to 4 Mbits. This is a PROM programmer adapter for the PD75P3036GC used by connecting to a PG-1500. This is a PROM programmer adapter for the PD75P3036GK used by connecting to a PG-1500. This is a PROM programmer adapter for the PD75P3036KK-T used by connecting to a PG1500. Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on host machine. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note 2 IBM PC/AT or compatible Refer to "OS for IBM PCs" Supply medium 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HD 5-inch 2HC Part No. (name) PA-75P328GC PA-75P336GK * Software PA-75P3036KK-T Note 1 PG-1500 controller S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500 * Notes 1. Under development 2. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above. 57 PD75P3036 Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the PD75P3036. Various system configurations using these in-circuit emulators are listed below. Hardware IE-75000-RNote 1 The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. For development of the PD75P3036, the IE-75000-R is used with optional emulation board (IE75300-R-EM) and emulation probe (EP-753036GC-R or EP-753036GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. The IE-75000-R includes a connected emulation board (IE-75000-R-EM). The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products. The IE-75001-R is used with optional emulation board (IE-75300-R-EM) and emulation probe (EP-753036GC-R or EP-753036GK-R). Highly efficient debugging can be performed when connected to host machine and PROM programmer. This is an emulation board for evaluating application systems using the PD75P3036. It is used in combination with the IE-75000-R or IE-75001-R. This is an emulation probe for the PD75P3036GC. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes an 80-pin conversion socket (EV-9200GC-80) to facilitate connections with target system. This is an emulation probe for the PD75P3036GK. When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM. It includes an 80-pin conversion adapter (EV-9500GK-80) to facilitate connections with target system. This program can control the IE-75000-R or IE-75001-R on a host machine when connected to the IE-75000-R or IE-75001-R via an RS-232-C and Centronics interface. Host machine OS PC-9800 Series MS-DOS Ver.3.30 to Ver.6.2Note 3 IBM PC/AT or compatible Refer to "OS for IBM PCs" Supply medium 3.5-inch 2HD 5-inch 2HD 3.5-inch 2HC 5-inch 2HC Part No. (name) IE-75001-R IE-75300-R-EMNote 2 EP-75336GC-R EV-9200GC-80 EP-75336GK-R EV-9500GK-80 Software IE control program S5A13IE75X S5A10IE75X S7B13IE75X S7B10IE75X * Notes 1. This is a maintenance product. 2. The IE-75300-R-EM is sold separately. 3. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function. Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described above. 2. The PD753036 and 75P3036 are commonly referred to as the PD753036 Subseries. 58 PD75P3036 OS for IBM PCs The following operating systems for the IBM PC are supported. OS Version Ver.5.02 to Ver.6.3 J6.1/V to J6.3/V MS-DOS Ver.5.0 to Ver.6.22 5.0/V to 6.2/V IBM DOSTM J5.02/V * * Caution PC DOS TM Ver. 5.0 or later includes a task swapping function, but this software is not able to use that function. 59 PD75P3036 * APPENDIX C. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Device Document Japanese Document No. English U11575E (this document) Planned U10201E -- U10453E PD75P3036 Data Sheet PD753036 Data Sheet PD753036 User's Manual PD753036 Instruction Table 75XL Series Selection Guide U11575J U11353J U10201J IEM-5063 U10453J Documents Related to Development Tools Document Japanese Hardware IE-75000-R/IE-75001-R User's Manual IE-75300-R-EM User's Manual EP-75336GC/GK-R User's Manual PG-1500 User's Manual Software RA75X Assembler Package User's Manual PG-1500 Controller User's Manual Operation Language PC-9800 Series (MS-DOS) base IBM PC Series (PC DOS) base EEU-5008 U10540E EEU-846 U11354J U10644J EEU-651 EEU-731 EEU-730 EEU-704 Document No. English EEU-1416 EEU-1493 U10644E EEU-1335 EEU-1346 EEU-1363 EEU-1291 Other Related Documents Document Japanese IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcomputer - Related Product Guide - Third Party Products - C10943X C10535J C11531J C10983J MEM-539 MEI-603 MEI-604 MEI-1202 -- C10535E C11531E C10983E -- Document No. English Caution The related documents listed above are subject to change without notice. Be sure to use the latest documents for designing, etc. 60 PD75P3036 [MEMO] 61 PD75P3036 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 62 PD75P3036 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 63 PD75P3036 MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC DOS, and PC/AT are trademarks of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 64 |
Price & Availability of UPD75P3036
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |